1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to electrode structure comprising upper and lower layers that are superposed on another, and to a contact hole structure in the electrode structure.
2. Description of the Prior Art
In recent years, semiconductor devices having an increased number of functions have been developed and a demand has arisen for heterogeneous devices in which a memory circuit and a logic circuit or an analog circuit are integrated at a high density with accuracy. Capacitor elements formed with higher density and higher precision are necessary, for example, for analog circuits in such heterogeneous devices. Also, it is necessary to mount a boosting circuit in a nonvolatile semiconductor storage device such as an electrically erasable programmable read-only memory (EEPROM) or a flash memory. A capacitor element of a large area is required as a component of a charge pump circuit constituting the boosting circuit. It is necessary to construct such a capacitor element in such a manner that electrode layers are laid one on another to form opposed electrodes, and each of the opposed electrodes is connected to wiring via a contact hole.
Various techniques, e.g., those disclosed in Japanese Patent Laid-open Publication Nos. 11-30774 and 10-004179 have been proposed as a method for forming the capacitor element in the above-described flash memory. Such conventional techniques will be described with reference to FIGS. 4, 5, and 6. In these figures, a lower layer electrode compared with an electrode in accordance with the present invention is indicated by hatching to be clearly recognized.
FIGS. 4A and 4B are a plan view and a cross-sectional view, respectively, of a first example of the conventional capacitor element. The cross-sectional view of FIG. 4B is taken along the line X1-X2 in FIG. 4A.
As shown in FIGS. 4A and 4B, an element separation insulating film 101 is formed on a silicon substrate 100, and a lower layer electrode 102 is formed by patterning on the element separation insulating film 101. The lower layer electrode 102 is formed from polycrystalline silicon containing an impurity. A capacitor insulating film 103 is formed on the surface of the lower layer electrode 102. An upper layer electrode 104 is formed by patterning so as to cover the lower layer electrode 102 and the capacitor insulating film 103. The upper layer electrode 104 is also formed from polycrystalline silicon containing an impurity.
An interlayer insulating film 105 is then deposited on the entire surface by chemical vapor deposition (CVD) and the surface of the insulating film 105 is flattened by chemical mechanical polishing (CMP). A lower layer electrode contact hole 106 is formed in a predetermined region of the interlayer insulating film 105. A plurality of upper layer electrode contact holes 107 and 107a are also formed, as shown in FIGS. 4A and 4B. Specifically, the upper layer electrode contact holes 107 and 107a are formed in the region right above the lower layer electrode 102.
Plugs (not shown) are formed so as to fill the lower layer electrode contact hole 106 and the upper layer electrode contact holes 107 and 107a and are electrically connected to wiring points (not shown), thus forming the capacitor element.
FIGS. 5A and 5B are a plan view and a cross-sectional view, respectively, of a second example of the conventional capacitor element. The cross-sectional view of FIG. 5B is taken along the line Y1-Y2 in FIG. 5A. A major difference of the second example of the conventional capacitor element from the first example resides in that a silicide is formed as a low-resistance portion in the surface of the above-described upper layer electrode of the first example. FIG. 6 schematically shows in section the structure of a floating-gate MOS transistor and an ordinary MOS transistor for explanation of this silicification.
As shown in FIGS. 5A and 5B, an element separation insulating film 201 is formed on a silicon substrate 200 and a lower layer electrode 202 is formed by patterning, as in the first example of the conventional capacitor element. The lower layer electrode 202 is formed from polycrystalline silicon containing an impurity, and a silicide layer 202a is formed as a portion of the lower layer electrode 202. A capacitor insulating film 203 is formed on the surface of the lower layer electrode 202. An upper layer electrode 206 is formed in a multilayer structure such that a polycrystalline silicon layer 204 and a silicide layer 205 are formed by patterning so as to cover the lower layer electrode 202 and the capacitor insulating film 203. A side wall insulating film 207 is formed on patterned ends of the upper layer electrode 206. This side wall insulating film 207 is formed of a silicon oxidation film. A side wall insulating film 208 is formed on stepped portions of the polycrystalline silicon layer 204 formed at ends of the lower layer electrode 202, as shown in FIG. 5B. The formation of the silicide layer and the side wall insulating films will be described in detail with reference to FIG. 6.
An interlayer insulating film 209 is formed on the entire surface, as is that in the first example of the conventional capacitor element. Further, a lower layer electrode contact hole 210 is formed in a predetermined region of the interlayer insulating film 209. A plurality of upper layer electrode contact holes 211 and 211a are also formed, as shown in FIGS. 5A and 5B. Specifically, the upper layer electrode contact holes 211 and 211a are formed off the region right above the lower layer electrode 202.
Plugs are formed so as to fill the lower layer electrode contact hole 210 and the upper layer electrode contact holes 211 and 211a and are electrically connected to wiring points, as are those in the first example of the conventional capacitor element. The second example of the conventional capacitor element is thus formed.
The above-mentioned silicification will next be described. FIG. 6 schematically shows in section the structure of a floating-gate MOS transistor and an ordinary MOS transistor. The capacitor element shown in FIGS. 5A and 5B is formed on the silicon substrate simultaneously with the floating-gate MOS transistor and the ordinary MOS transistor shown in FIG. 6.
That is, device separation insulating film 201 is formed on silicon substrate 200, and a floating-gate electrode 212 is formed in the floating-gate MOS transistor with an tunnel oxide film interposed between the substrate and the floating-gate electrode 212. A polycrystalline silicon layer 213 is formed on the floating-gate electrode 212 with an interelectrode insulating film interposed therebetween, and a silicide layer 214 is formed on the polycrystalline silicon layer 213. The polycrystalline silicon layer 213 and the silicide layer 214 forms for a control gate electrode 215. A side wall insulating film 216 is formed on side wall surfaces of the floating-gate electrode 212 and the control gate electrode 215. The electrodes, etc., are thus constructed. Further, a diffusion layer 217 for forming source and drain regions of the floating-gate MOS transistor is formed and a silicide layer 218 is formed in an upper portion of the diffusion layer 217.
Similarly, in the ordinary MOS transistor, a polycrystalline silicon layer 220 is formed on a gate insulating film 219 and a silicide layer 221 is formed in an upper portion of the polycrystalline silicon layer 220. The polycrystalline silicon layer 220 and the silicide layer 221 form a gate electrode 222. A side wall insulating film 223 is formed on side wall surfaces of the gate electrode 222. Further, a diffusion layer 224 for forming source and drain regions of the MOS transistor is formed and a silicide layer 225 is formed in an upper portion of the diffusion layer 224.
Contact holes 226 for the floating-gate MOS transistor and contact holes 227 for the ordinary MOS transistor are formed in predetermined regions of the interlayer insulating film 209 covering the entire surface.
The lower layer electrode 202 of the capacitor element shown in FIG. 5 is formed of the same polycrystalline silicon film as the floating gate electrode 212 of the floating-gate MOS transistor. The polycrystalline silicon layer 204 constituting the upper layer electrode 206 is formed of the same polycrystalline silicon film as the polycrystalline silicon layer 213 of the floating-gate MOS transistor and the polycrystalline silicon layer 220 of the ordinary MOS transistor. The silicide layer 205 or 202a is formed simultaneously with the silicide layers 214 and 218 of the floating-gate MOS transistor and the silicide layers 221 and 225 of the ordinary MOS transistor by a silicification technique for silicification of these silicide layers. In this silicification technique, forming of side wall insulating films 216 and 223 is necessary. Therefore side wall insulating films 207 and 208 are necessarily formed on the patterned ends or stepped portions of the upper layer electrode 206 shown in FIGS. 5A and 5B. Also, the lower electrode contact hole 210 and the upper layer electrode contact holes 211 and 211a of the capacitor element shown in FIGS. 5A and 5B are formed by the same etching process as that for forming the contact holes 226 of the floating-gate MOS transistor and the contact holes 227 of the ordinary MOS transistor.
The above-described conventional techniques for forming capacitor elements have problems described below. In the process of manufacturing the first example of the conventional capacitor element described above with reference to FIGS. 4A and 4B, the insulation between the upper layer electrode 104 and the lower layer electrode 102 becomes deteriorated. The following is a possible explanation of this phenomenon. In the first example of the conventional capacitor element, the upper layer electrode contact holes 107 and 107a are formed in the region above the lower layer electrode 102. After the formation of these contact holes, native oxide film is removed by a process step using a dilute hydrofluoric acid solution in order to reduce the resistance of contact to the plugs filling the contact holes. In this process step, however, the dilute hydrofluoric acid solution permeates through grain boundaries in the polycrystalline silicon film constituting the upper layer electrode 104 to corrode the capacitor insulating film 103 below the upperlayer electrode 104. The insulating effect of portions of the capacitor insulating film below the upper layer electrode contact holes 107 and 107a is reduced by this corrosion.
In the second example of the conventional capacitor element described above with reference to FIGS. 5A and 5B, the upper layer electrode contact holes 211 and 211a are formed off the patterned area of the lower layer electrode 202 unlike those in the first example. Therefore the second example of the conventional capacitor element has no problem such as that described with respect to the first example. However, when the silicide layer 205 constituting the upper layer electrode 206 in the second example of the conventional capacitor element is formed, it cannot be formed entirely continuously, so that the resistance of the upper layer electrode 206 cannot be sufficiently reduced. That is, as shown in FIG. 5B, side wall insulating film 208 is necessarily formed on stepped portions of the polycrystalline silicon layer 204 that occur at the ends of the lower layer electrode 202 pattern. In the above-described silicification step, the silicide layer cannot be formed in the region covered with this side wall insulating film 298. A reduction in the effect of reducing the resistance due to failure to completely form the silicide layer leads to a considerable reduction in the performance of a charge pump circuit formed by using this capacitor element.
1. Objects of the Invention
An object of the present invention is to provide a semiconductor device in which the performance and reliability of insulation with an insulating film formed between a lower layer electrode and an upper layer electrode in a capacitor element for example are high. Another object of the present invention is to provide a semiconductor device in which the resistance of the above-described upper layer electrode or lower layer electrode can be reduced highly controllably.
2. Summary of the Invention
According to the present invention, there is provided a semiconductor device in which a first electrode and a second electrode are formed in this order in a multilayer structure on a semiconductor substrate with an insulating layer interposed between the first and second electrodes, a contact hole for connection of the second electrode to a wiring layer formed above the second electrode being formed at a position above a separated region of the first electrode formed separately from a main region of the first electrode.